External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

13.7.2.2.2. Adding Interfaces to an Design Example

To create a design containing two or more interfaces, complete the following steps.
  1. Repeat the steps of the Generating a Design Example with the Debug Toolkit procedure for as many interfaces as required in your design.
  2. Choose one of the generated design examples to add all the other interfaces to. This integrated design is used in the final project.
  3. Each of the generated designs contains an /ip directory, in which several files having .ip extension reside. For each additional interface, move the following files into the final project's /ip directory, and rename them to distinguish them from other existing files in that directory:
    1. ed_synth_s10_0.ip
    2. ed_synth_tg.ip
    3. ed_synth_ninit_done.ip
    Figure 123. Existing Connections Before Adding a Second Design Example
  4. Open the ed_synth.qsys file of the final project in the Platform Designer.
  5. The IP variants that you have copied into the final project directory should now appear under the Existing IP Variants section of the IP Catalog. Add these IP variants to your system and connect them to each other, using the original design example as reference.
  6. If no two EMIF IPs in your design share an I/O column, skip ahead to step 8; otherwise, proceed as follows:
    1. One EMIF IP in each column used must be at the head of the daisy-chain; to do this, set the following parameters in this EMIF IP:
      • Set Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port to Add EMIF Debug Interface.
      • Select Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port.
    2. One EMIF IP in each column used must be at the end of the daisy-chain; to do this, set the following parameters in this EMIF IP:
      • Set Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port to Export.
      • Deselect Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port.
    3. Configure every additional EMIF IP as follows:
      • Set Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port to Export.
      • Select Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port.
  7. Connect any daisy-chained EMIF IPs in your design. To do this, make connections from a cal_debug_out interface on one EMIF to the cal_debug interface on another EMIF.
    Figure 124. Connections for a Second EMIF Design Example
  8. Ensure you have ported any pin assignments over to the final design.
  9. After the system is connected, you can generate HDL and compile your design.

Did you find the information on this page useful?

Characters remaining:

Feedback Message