External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

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ID 683741
Date 3/11/2022
Public
Document Table of Contents

12.3. Data Transfer

The following methods of data transfer reduce the efficiency of your controller:
  • Performing individual read or write accesses is less efficient.
  • Switching between read and write operation has a negative impact on the efficiency of the controller.
  • Performing read or write operations from different rows within a bank or in a different bank—if the bank and a row you are accessing is not already open—also affects the efficiency of your controller.

The following figure shows an example of changing the row in the same bank.

Figure 100. Changing Row in the Same Bank


The following sequence of events describes the above figure:

  1. You have to wait tWR time before giving the precharge command
  2. You then wait tRP time to give the activate command.
Note: The tWR and tRP values depend on memory timing parameters.

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