External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.1.1.14. afi_half_clk for DDR3

AFI half-rate clock interface

Table 25.  Interface: afi_half_clkInterface type: Clock Output
Port Name Direction Description
afi_half_clk Output Clock running at half the frequency of the AFI clock afi_clk

Did you find the information on this page useful?

Characters remaining:

Feedback Message