5.3. Simulation Walkthrough
For a given design on a given board, the latency found may differ by one clock cycle (for full-rate designs) or two clock cycles (for half-rate designs) upon resetting the board. Different boards can also show different latencies even with the same design.
The Intel® Stratix® 10 EMIF IP supports functional simulation only. Functional simulation is supported at the RTL level after generating a post-fit functional simulation netlist. The post-fit netlist for designs that contain Intel® Stratix® 10 EMIF IP is a hybrid of the gate level (for FPGA core) and RTL level (for the external memory interface IP). You should validate the functional operation of your design using RTL simulation, and the timing of your design using timing analysis.
The Intel® Stratix® 10 EMIF IP supports functional simulation through the design example using the Traffic Generator (TG1) or the Configurable Traffic Generator 2.0 (TG2). (For information on TG2, refer to Using the Configurable Traffic Generator (TG2). Functional simulation using TG2 is allowed only with default traffic pattern, where TG2 runs a default traffic pattern after reset instead of waiting for user configuration for TG2, as in user mode. Do not select Bypass the default traffic mode when creating a design example for functional simulation using TG2.
To perform functional simulation for an Intel® Stratix® 10 EMIF IP design example, locate the design example files in the design example directory.
You can use the IP functional simulation model with any supported VHDL or Verilog HDL simulator.
After you have generated the memory IP, you can locate multiple file sets for various supported simulations in the sim/ed_sim subdirectory. For more information about the EMIF simulation design example, refer to the Intel® Stratix® 10 External Memory Interfaces IP Design Example User Guide.
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