External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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10.3.1.6. Pin Guidelines for Intel® Stratix® 10 EMIF IP

The Intel® Stratix® 10 device contains up to three I/O columns that can be used by external memory interfaces. The Intel® Stratix® 10 I/O subsystem resides in the I/O columns. Each column contains multiple I/O banks, each of which consists of four I/O lanes. An I/O lane is a group of twelve I/O ports.

The I/O column, I/O bank, I/O lane, adjacent I/O bank, and pairing pin for every physical I/O pin can be uniquely identified using the Bank Number and Index within I/O Bank values which are defined in each Intel® Stratix® 10 device pin-out file.

  • The numeric component of the Bank Number value identifies the I/O column, while the letter represents the I/O bank.
  • The Index within I/O Bank value falls within one of the following ranges: 0 to 11, 12 to 23, 24 to 35, or 36 to 47, and represents I/O lanes 1, 2, 3, and 4, respectively.
  • To determine if I/O banks are adjacent, you can refer to the I/O Pin Counts tables located in the Intel® Stratix® 10 General Purpose I/O User Guide . You can always assume I/O banks are adjacent within an I/O column except in the following conditions:

    • When an I/O bank is not bonded out on the package (contains the '-' symbol in the I/O table).
    • An I/O bank does not contain 48 pins, indicating it is only partially bonded out.
  • The pairing pin for an I/O pin is located in the same I/O bank. You can identify the pairing pin by adding one to its Index within I/O Bank number (if it is an even number), or by subtracting one from its Index within I/O Bank number (if it is an odd number).

For example, a physical pin with a Bank Number of 2M and Index within I/O Bank of 22, indicates that the pin resides in I/O lane 2, in I/O bank 2M, in column 2. The adjacent I/O banks are 2L and 2N. The pairing pin for this physical pin is the pin with an Index within I/O Bank of 23 and Bank Number of 2M.

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