External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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8.2.1. Equations for QDRII, QDRII+, and QDRII+ Xtreme Board Skew Parameters

Table 284.  Board Skew Parameter Equations
Parameter Description/Equation
Maximum system skew within address/command bus
The largest skew between the address and command signals. Enter combined board and package skew.
Average delay difference between address/command and K The average delay difference between the address and command signals and the K signal, calculated by averaging the longest and smallest Address/Command signal delay minus the K delay. Positive values represent address and command signals that are longer than K signals and negative values represent address and command signals that are shorter than K signals. The Quartus Prime software uses this skew to optimize the delay of the address and command signals to have appropriate setup and hold margins.
where n is the number of K clocks.
Maximum board skew within Q group The largest skew between all Q pins in a Q group. Enter your board skew only. Package skew is calculated automatically, based on the memory interface configuration, and added to this value. This value affects the read capture and write margins.
where g is the number of Q group.
Maximum board skew within D group

The largest skew between all D and BWS# pins in a D group. Enter your board skew only. Package skew is calculated automatically, based on the memory interface configuration, and added to this value. This value affects the read capture and write margins.

where g is the number of D group.
Maximum K delay to device
where n is the number of K clocks.

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