External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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8.4.1. QDR II SRAM Configurations

The QDR II SRAM Controller for Intel® Stratix® 10 EMIF IP supports interfaces with a single device, and two devices in a width expansion configuration up to maximum width of 72 bits.

The following figure shows the main signal connections between the FPGA and a single QDR II SRAM component.

Figure 79. Configuration With A Single QDR II SRAM Component


The following figure shows the main signal connections between the FPGA and two QDR II SRAM components in a width expansion configuration.

Figure 80. Configuration With Two QDR II SRAM Components In A Width Expansion Configuration


The following figure shows the detailed balanced topology recommended for the address and command signals in the width expansion configuration.

Figure 81. External Parallel Termination for Balanced Topology


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