External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
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7.1.7. Intel Stratix 10 EMIF IP DDR4 Parameters: Controller

Table 235.  Group: Controller / Low Power Mode
Display Name Description
Enable Auto Power-Down Enable this parameter to have the controller automatically place the memory device into power-down mode after a specified number of idle controller clock cycles. The idle wait time is configurable. All ranks must be idle to enter auto power-down. (Identifier: CTRL_DDR4_AUTO_POWER_DOWN_EN)
Auto Power-Down Cycles Specifies the number of idle controller cycles after which the memory device is placed into power-down mode. You can configure the idle waiting time. The supported range for number of cycles is from 1 to 65534. (Identifier: CTRL_DDR4_AUTO_POWER_DOWN_CYCS)
Table 236.  Group: Controller / Efficiency
Display Name Description
Enable User Refresh Control When enabled, user logic has complete control and is responsible for issuing adaquate refresh commands to the memory devices, via the MMR interface. This feature provides increased control over worst-case read latency and enables you to issue refresh bursts during idle periods. (Identifier: CTRL_DDR4_USER_REFRESH_EN)
Enable Auto-Precharge Control Select this parameter to enable the auto-precharge control on the controller top level. If you assert the auto-precharge control signal while requesting a read or write burst, you can specify whether the controller should close (auto-precharge) the currently open page at the end of the read or write burst, potentially making a future access to a different page of the same bank faster. (Identifier: CTRL_DDR4_AUTO_PRECHARGE_EN)
Address Ordering Controls the mapping between Avalon addresses and memory device addresses. By changing the value of this parameter, you can change the mappings between the Avalon-MM address and the DRAM address. (CS = chip select, CID = chip ID in 3DS/TSV devices, BG = bank group address, Bank = bank address, Row = row address, Col = column address) (Identifier: CTRL_DDR4_ADDR_ORDER_ENUM)
Enable Reordering Enable this parameter to allow the controller to perform command and data reordering. Reordering can improve efficiency by reducing bus turnaround time and row/bank switching time. Data reordering allows the single-port memory controller to change the order of read and write commands to achieve highest efficiency. Command reordering allows the controller to issue bank management commands early based on incoming patterns, so that the desired row in memory is already open when the command reaches the memory interface. For more information, refer to the Data Reordering topic in the EMIF Handbook. (Identifier: CTRL_DDR4_REORDER_EN)
Starvation limit for each command Specifies the number of commands that can be served before a waiting command is served. The controller employs a counter to ensure that all requests are served after a pre-defined interval -- this ensures that low priority requests are not ignored, when doing data reordering for efficiency. The valid range for this parameter is from 1 to 63. For more information, refer to the Starvation Control topic in the EMIF Handbook. (Identifier: CTRL_DDR4_STARVE_LIMIT)
Enable Command Priority Control Select this parameter to enable user-requested command priority control on the controller top level. This parameter instructs the controller to treat a read or write request as high-priority. The controller attempts to fill high-priority requests sooner, to reduce latency. Connect this interface to the conduit of your logic block that determines when the external memory interface IP treats the read or write request as a high-priority command. (Identifier: CTRL_DDR4_USER_PRIORITY_EN)
Table 237.  Group: Controller / Configuration, Status and Error Handling
Display Name Description
Enable Memory-Mapped Configuration and Status Register (MMR) Interface Enable this parameter to change or read memory timing parameters, memory address size, mode register settings, controller status, and request sideband operations. (Identifier: CTRL_DDR4_MMR_EN)
Enable Error Detection and Correction Logic with ECC Enables error-correction code (ECC) for single-bit error correction and double-bit error detection. ECC is implemented as soft logic. (Identifier: CTRL_DDR4_ECC_EN)
Enable Auto Error Correction to External Memory Specifies that the controller automatically schedule and perform a write back to the external memory when a single-bit error is detected. Regardless of whether the option is enabled or disabled, the ECC feature always corrects single-bit errors before returning the read data to user logic. (Identifier: CTRL_DDR4_ECC_AUTO_CORRECTION_EN)
Enable ctrl_ecc_readdataerror signal to indicate uncorrectable data errors Select this option to enable the ctrl_ecc_readdataerror signal on the controller top level. The signal has the same timing as the read data valid signal of the Controller Avalon Memory-Mapped interface, and is asserted high to indicate that the read data returned by the Controller in the same cycle contains errors uncorrectable by the ECC logic. (Identifier: CTRL_DDR4_ECC_READDATAERROR_EN)
Export error-correction code (ECC) status ports Enable this parameter to export ECC status ports.
Table 238.  Group: Controller / Data Bus Turnaround Time
Display Name Description
Additional read-to-write turnaround time (same rank) Specifies additional number of idle controller (not DRAM) cycles when switching the data bus from a read to a write within the same logical rank. This can help resolve bus contention problems specific to your board topology. The value is added to the default which is calculated automatically. Use the default setting unless you suspect a problem exists. (Identifier: CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS)
Additional write-to-read turnaround time (same rank) Specifies additional number of idle controller (not DRAM) cycles when switching the data bus from a write to a read within the same logical rank. This can help resolve bus contention problems specific to your board topology. The value is added to the default which is calculated automatically. Use the default setting unless you suspect a problem exists. (Identifier: CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS)
Additional read-to-read turnaround time (different ranks) Specifies additional number of idle controller (not DRAM) cycles when switching the data bus from a read of one logical rank to a read of another logical rank. This can resolve bus contention problems specific to your board topology. The value is added to the default which is calculated automatically. Use the default setting unless you suspect a problem exists. (Identifier: CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS)
Additional read-to-write turnaround time (different ranks) Specifies additional number of idle controller (not DRAM) cycles when switching the data bus from a read of one logical rank to a write of another logical rank. This can help resolve bus contention problems specific to your board topology. The value is added to the default which is calculated automatically. Use the default setting unless you suspect a problem exists. (Identifier: CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS)
Additional write-to-write turnaround time (different ranks) Specifies additional number of idle controller (not DRAM) cycles when switching the data bus from a write of one logical rank to a write of another logical rank. This can help resolve bus contention problems specific to your board topology. The value is added to the default which is calculated automatically. Use the default setting unless you suspect a problem exists. (Identifier: CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS)
Additional write-to-read turnaround time (different ranks) Specifies additional number of idle controller (not DRAM) cycles when switching the data bus from a write of one logical rank to a read of another logical rank. This can help resolve bus contention problems specific to your board topology. The value is added to the default which is calculated automatically. Use the default setting unless you suspect a problem exists. (Identifier: CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS)

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