External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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3.1.7. Intel® Stratix® 10 EMIF Architecture: PHY Clock Tree

Dedicated high-speed clock networks drive I/Os in Intel® Stratix® 10 EMIF. Each PHY clock network spans only one bank.

The relatively short span of the PHY clock trees results in low jitter and low duty-cycle distortion, maximizing the data valid window.

The PHY clock tree in Intel® Stratix® 10 devices can run as fast as 1.3 GHz. All Intel® Stratix® 10 external memory interfaces use the PHY clock trees.

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