External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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4.1.1.16. emif_usr_reset_n for DDR3

User clock domain reset interface

Table 27.  Interface: emif_usr_reset_nInterface type: Reset Output
Port Name Direction Description
emif_usr_reset_n Output Reset for the user clock domain. Asynchronous assertion and synchronous deassertion

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