External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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13.9.1. Enabling the Traffic Generator in a Design Example

You can enable the traffic generator from the Diagnostics tab in the EMIF parameter editor.

To enable the traffic generator, turn on Use configurable Avalon traffic generator 2.0 on the Diagnostics tab.

Figure 169. 
  • You may choose to disable the default traffic pattern stage or the user-configured traffic stage, but you must have at least one stage enabled. For information on these stages, refer to Default Traffic Pattern and User-Configured Traffic Pattern.
  • The TG2 test duration parameter applies only to the default traffic pattern. You may choose a test duration of short, medium, or infinite.
  • You may choose either of two values for the TG2 Configuration Interface Mode parameter:

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