External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

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ID 683741
Date 3/11/2022
Public
Document Table of Contents

13.1. Interface Configuration Performance Issues

There are many interface combinations and configurations possible in an Intel® design, therefore it is impractical for Intel® to explicitly state the achievable fMAX for every combination.

Intel® seeks to provide guidance on typical performance, but this data is subject to memory component timing characteristics, interface widths, depths directly affecting timing deration requirements, and the achieved skew and timing numbers for a specific PCB.

FPGA timing issues should generally not be affected by interface loading or layout characteristics. In general, the Intel® performance figures for any given device family and speed-grade combination should usually be achievable.

To resolve FPGA (PHY and PHY reset) timing issues, refer to the Analyzing Timing of Memory IP chapter.

Achievable interface timing (address and command, half-rate address and command, read and write capture) is directly affected by any layout issues (skew), loading issues (deration), signal integrity issues (crosstalk timing deration), and component speed grades (memory timing size and tolerance). Intel® performance figures are typically stated for the default (single rank, unbuffered DIMM) case. Intel® provides additional expected performance data where possible, but the fMAX is not achievable in all configurations. Intel® recommends that you optimize the following items whenever interface timing issues occur:

  • Improve PCB layout tolerances
  • Use a faster speed grade of memory component
  • Ensure that the interface is fully and correctly terminated
  • Reduce the loading (reduce the deration factor)

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