External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public
Document Table of Contents

13.7.1.8.1. Determining Margin

The Driver Margining feature lets you measure margins on your EMIF IP interface using a driver with arbitrary traffic patterns.
The Driver Margining feature is available only for DDR3 and DDR4 interfaces, when ECC is not enabled.
  1. Establish a connection to the desired interface and ensure that it has calibrated successfully.
  2. Select Driver Margining from the Commands folder under the target interface connection.
  3. Select the appropriate In-System Sources/Probes using the drop-down menus.
  4. If required, set additional options in the Advanced Options section:
    • Margining is performed on all ranks together.
    • Step size specifies the granularity of the driver margining process. Larger step sizes allow faster margining but reduced accuracy. It is recommended to omit this setting.
    • Adjust delays after margining causes delay settings to be adjusted to the center of the window based on driver margining results.
    • The Margin Read, Write, Write DM, and DBI checkboxes allow you to control which settings are tested during driver margining. You can uncheck boxes to allow driver margining to complete more quickly.
  5. Click OK to run the tests.
    The toolkit measures margins for DQ read/write and DM. The process may take several minutes, depending on the margin size and the duration of the driver tests. The test results are available in the Margin Report.

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