External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

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ID 683741
Date 3/11/2022
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4.1.1.3. pll_ref_clk for DDR3

PLL reference clock input

Table 14.  Interface: pll_ref_clkInterface type: Clock Input
Port Name Direction Description
pll_ref_clk Input PLL reference clock input

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