External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

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ID 683741
Date 3/11/2022
Public
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3.7. Intel® Stratix® 10 EMIF for Hard Processor Subsystem

The Intel® Stratix® 10 EMIF IP can enable the Intel® Stratix® 10 Hard Processor Subsystem (HPS) to access external DRAM memory devices.

To enable connectivity between the Intel® Stratix® 10 HPS and the Intel® Stratix® 10 EMIF IP, you must create and configure an instance of the Intel® Stratix® 10 External Memory Interface for HPS IP core, and use Platform Designer to connect it to the Intel® Stratix® 10 Hard Processor Subsystem instance in your system.

Supported Modes

The Intel® Stratix® 10 Hard Processor Subsystem is compatible with the following external memory configurations:

Table 10.   Intel® Stratix® 10 Hard Processor Subsystem Compatibility
Protocol DDR3, DDR4
Maximum memory clock frequency

DDR3: 933 MHz

DDR4: 1200 MHz

Configuration Hard PHY with hard memory controller
Clock rate of PHY and hard memory controller Half-rate
Data width (without ECC) 16-bit, 32-bit, 64-bit
Data width (with ECC) 24-bit, 40-bit, 72-bit
DQ width per group x8
Maximum number of I/O lanes for address/command 3
Memory format Discrete, UDIMM, SODIMM, RDIMM
Ranks / CS# width Up to 2
Note: You must provide a free running and stable reference clock source to external memory interface cores before the start of device configuration.

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