External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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13.7.4. Legacy Efficiency Monitor and Protocol Checker

For designs created prior to the Intel® Quartus® Prime software version 20.3, you can use the Legacy Efficiency Monitor and Protocol Checker to measure traffic efficiency on the Avalon® -MM bus between the controller and user logic. For newer designs created in the Intel® Quartus® Prime software version 20.3 or later, use the new Efficiency Monitor.

The Legacy Efficiency Monitor and Protocol Checker measures read latencies, and checks the legality of Avalon® commands passed from the master.

For Intel® Stratix® 10 devices, the Legacy Efficiency Monitor and Protocol Checker is available for the following configurations:

  • DDR4 with hard PHY and hard controller
  • QDR-IV with hard PHY and soft controller
The Legacy Efficiency Monitor and Protocol Checker is not available for PHY-only designs.

Efficiency Monitor

The Efficiency Monitor counts command transfers and wait times on the controller input and passes that information to the EMIF Debug Toolkit over an Avalon® slave port. This summary of read and write throughput may be useful to you when experimenting with advanced controller settings, such as command and data reordering.

Protocol Checker

The Protocol Checker checks the legality of commands on the controller’s input interface against Avalon® interface specifications. If the Protocol Checker detects an illegal command, it sets a flag in a register on an Avalon® slave port.

Read Latency Counter

The Read Latency Counter measures the minimum and maximum wait times for read commands to be serviced on the Avalon® bus. Each read command is time-stamped and placed into a FIFO buffer upon arrival. The Read Latency Counter determines latency by comparing the time stamp to the current time when the master receives the first beat of the returned read data.

Note: Be aware that including the Legacy Efficiency Monitor and Protocol Checker when you generate your IP may make it more difficult to achieve timing closure.

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