External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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4.2.1. AFI Clock and Reset Signals

The AFI interface provides up to two clock signals and an asynchronous reset signal.
Table 163.  Clock and Reset Signals 

Signal Name

Direction

Width

Description

afi_clk

Output

1

Clock with which all data exchanged on the AFI bus is synchronized. In general, this clock is referred to as full-rate, half-rate, or quarter-rate, depending on the ratio between the frequency of this clock and the frequency of the memory device clock.

afi_half_clk

Output

1

Clock signal that runs at half the speed of the afi_clk. The controller uses this signal when the half-rate bridge feature is in use. This signal is optional.

afi_reset_n

Output

1

Asynchronous reset output signal. You must synchronize this signal to the clock domain in which you use it.

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