External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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13.7.1.4. Configuring Your EMIF IP for Use with the Legacy Debug Toolkit

The Intel® Stratix® 10 EMIF Debug Interface IP core contains the access point through which the Legacy EMIF Debug Toolkit reads calibration data collected by the Nios II sequencer.

Connecting an EMIF IP Core to an Intel® Stratix® 10 EMIF Debug Interface

For the EMIF Debug Toolkit to access the calibration data for a Intel® Stratix® 10 EMIF IP core, you must connect one of the EMIF cores in each I/O column to a Intel® Stratix® 10 EMIF Debug Interface IP core. Subsequent EMIF IP cores in the same column must connect in a daisy chain to the first.

There are two ways that you can add the Intel® Stratix® 10 EMIF Debug Interface IP core to your design:

  • When you generate your EMIF IP core, on the Diagnostics tab, select Add EMIF Debug Interface for the EMIF Debug Toolkit/On-Chip Debug Port; you do not have to separately instantiate a Intel® Stratix® 10 EMIF Debug Interface core. This method does not export an Avalon® -MM slave port. You can use this method if you require only EMIF Debug Toolkit access to this I/O column; that is, if you do not require On-Chip Debug Port access, or PHYLite reconfiguration access.
  • When you generate your EMIF IP core, on the Diagnostics tab, select Export for the EMIF Debug Toolkit/On-Chip Debug Port. Then, separately instantiate an Intel® Stratix® 10 EMIF Debug Interface core and connect its to_ioaux interface to the cal_debug interface on the EMIF IP core. This method is appropriate if you want to also have On-Chip Debug Port access to this I/O column, or PHYLite reconfiguration access.

For each of the above methods, you must assign a unique interface ID for each external memory interface in the I/O column, to identify that interface in the Legacy Debug Toolkit. You can assign an interface ID using the dropdown list that appears when you enable the Debug Toolkit/On-Chip Debug Port option.

Connecting an EMIF IP Core and PHYLite Core

If you place any PHYLite cores with dynamic reconfiguration enabled into the same I/O column as an EMIF IP core, you should instantiate and connect the PHYLite cores in a similar way. See the Intel FPGA PhyLite for Parallel Interfaces IP Core User Guide for more information.

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