External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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3.3. Intel® Stratix® 10 EMIF Calibration

The calibration process compensates for skews and delays in the external memory interface.

The calibration process enables the system to compensate for the effects of factors such as the following:

  • Timing and electrical constraints, such as setup/hold time and Vref variations.
  • Circuit board and package factors, such as skew, fly-by effects, and manufacturing variations.
  • Environmental uncertainties, such as variations in voltage and temperature.
  • The demanding effects of small margins associated with high-speed operation.

For a given external memory interface, calibration occurs in parallel for all DQS groups and I/O banks. For an I/O column containing multiple external memory interfaces, there is no particular calibration order in relation to the interfaces; however, for a given SRAM Object File (.sof), calibration always occurs in the same order.

Note: The calibration process is intended to maximize margins for robust EMIF operation; it cannot compensate for an inadequate PCB layout.

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