External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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7.3.1. Equations for DDR4 Board Skew Parameters

Table 249.  Board Skew Parameter Equations
Parameter Description/Equation
Maximum CK delay to DIMM/device The delay of the longest CK trace from the FPGA to any DIMM/device.
Where n is the number of memory clock and r is the number rank of DIMM/device. For example in dual-rank DIMM implementation, if there are 2 pairs of memory clocks in each rank DIMM, the maximum CK delay is expressed by the following equation:
Maximum DQS delay to DIMM/device The delay of the longest DQS trace from the FPGA to the DIMM/device.
Where n is the number of DQS and r is the number of rank of DIMM/device. For example in dual-rank DIMM implementation, if there are 2 DQS in each rank