External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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7.3.1. Equations for DDR4 Board Skew Parameters

Table 249.  Board Skew Parameter Equations
Parameter Description/Equation
Maximum CK delay to DIMM/device The delay of the longest CK trace from the FPGA to any DIMM/device.
Where n is the number of memory clock and r is the number rank of DIMM/device. For example in dual-rank DIMM implementation, if there are 2 pairs of memory clocks in each rank DIMM, the maximum CK delay is expressed by the following equation:
Maximum DQS delay to DIMM/device The delay of the longest DQS trace from the FPGA to the DIMM/device.
Where n is the number of DQS and r is the number of rank of DIMM/device. For example in dual-rank DIMM implementation, if there are 2 DQS in each rank DIMM, the maximum DQS delay is expressed by the following equation:
Average delay difference between DQS and CK The average delay difference between the DQS signals and the CK signal, calculated by averaging the longest and smallest DQS delay minus the CK delay. Positive values represent DQS signals that are longer than CK signals and negative values represent DQS signals that are shorter than CK signals. The Quartus Prime software uses this skew to optimize the delay of the DQS signals for appropriate setup and hold margins.
Where n is the number of memory clock, m is the number of DQS, and r is the number of rank of DIMM/device.

When using discrete components, the calculation differs slightly. Find the minimum and maximum values for (DQS-CK) over all groups and then divide by 2. Calculate the (DQS-CK) for each DQS group, by using the appropriate CLK for that group.

For example, in a configuration with 5 x16 components, with each component having two DQS groups: To find the minimum and maximum, calculate the minimum and maximum of (DQS0 – CK0, DQS1 – CK0, DQS2 –CK1, DQS3 – CK1, and so forth) and then divide the result by 2.
Maximum Board skew within DQS group The largest skew between all DQ and DM pins in a DQS group. Enter your board skew only. Package skew is calculated automatically, based on the memory interface configuration, and added to this value. This value affects the read capture and write margins.
Maximum skew between DQS groups The largest skew between DQS signals in different DQS groups.
Maximum system skew within address/command bus
The largest skew between the address and command signals. Enter combined board and package skew. In the case of a component, find the maximum address/command and minimum address/command values across all component address signals.
Average delay difference between address/command and CK A value equal to the average of the longest and smallest address/command signal delays, minus the delay of the CK signal. The value can be positive or negative.

The average delay difference between the address/command and CK is expressed by the following equation:
where n is the number of memory clocks.
Maximum delay difference between DIMMs/devices The largest propagation delay on DQ signals between ranks. For example, in a two-rank configuration where you place DIMMs in different slots there is also a propagation delay for DQ signals going to and coming back from the furthest DIMM compared to the nearest DIMM. This parameter is applicable only when there is more than one rank.Maxr { max n,m [(DQn_r path delay– DQn_r+1 path delay), (DQSm_r path delay– DQSm_r+1 path delay)]}

Where n is the number of DQ, m is the number of DQS and r is number of rank of DIMM/device .

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