ID 683741
Date 3/11/2022
Public

## 5.3.6. Simulating the Design Example

This topic describes how to simulate the design example in Cadence, Synopsys* , Siemens EDA, and Aldec simulators.

To simulate the design example in the Intel® Quartus® Prime software using the Cadence simulator, follow these steps:

1. At the Linux* shell command prompt, change directory to sim\ed_sim\cadence
2. Run the simulation by typing the following command at the command prompt:
sh xcelium_setup.sh

To simulate the example design in the Intel® Quartus® Prime software using the Synopsys* simulator, follow these steps:

1. At the Linux* shell command prompt, change directory to sim\ed_sim\synopsys\vcsmx
2. Run the simulation by typing the following command at the command prompt:
sh vcsmx_setup.sh

To simulate the example design in the Intel® Quartus® Prime software using the Siemens EDA simulator, follow these steps:

1. At the Linux or Windows shell command prompt, change directory to sim\ed_sim\mentor
2. Execute the msim_setup.tcl script that automatically compiles and runs the simulation by typing the following command at the Linux or Windows command prompt:
vsim -do msim_setup.tcl

or

Type the following command at the ModelSim* command prompt:

do msim_setup.tcl


For more information about simulating the external memory interface using the Siemens EDA simulator, refer to the Simulating External Memory Interface IP With ModelSim chapter in the Intel® Stratix® 10 External Memory Interfaces IP Design Example User Guide.

Note: Intel does not provide the run.do file for the example design with the EMIF interface.

To simulate the example design in the Intel® Quartus® Prime software using the Aldec simulator, follow these steps:

1. At the Linux or Windows shell command prompt, change directory to sim\ed_sim\aldec
2. Execute the rivierapro_setup.tcl script that automatically compiles and runs the simulation by typing the following command at the Linux or Windows command prompt: vsim -do rivierapro.tcl
3. To compile and elaborate the design after the script loads, type ld_debug.
4. Type run -all to run the simulation.

For more information about simulation, refer to the Simulating Designs chapter in Volume 3 of the Intel® Quartus® Prime Handbook.

If your Intel® Quartus® Prime project appears to be configured correctly but the example testbench still fails, check the known issues on the Intel FPGA Knowledge Base before filing a service request.