External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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4.1.2. Intel Stratix 10 EMIF IP Interfaces for DDR4

The interfaces in the Intel Stratix 10 External Memory Interface IP each have signals that can be connected in Platform Designer. The following table lists the interfaces and corresponding interface types for DDR4.

Table 48.  Interfaces for DDR4
Interface Name Interface Type Description
local_reset_req Conduit Local reset request. Output signal from local_reset_combiner
local_reset_status Conduit Local reset status. Input signal to the local_reset_combiner
pll_ref_clk Clock Input PLL reference clock input
pll_locked Conduit PLL locked signal
pll_extra_clk_0 Clock Output Additional core clock 0
pll_extra_clk_1 Clock Output Additional core clock 1
pll_extra_clk_2 Clock Output Additional core clock 2
pll_extra_clk_3 Clock Output Additional core clock 3
ac_parity_err Output PORT_AC_PARITY_STATE_DESC
oct Conduit On-Chip Termination (OCT) interface
mem Conduit Interface between FPGA and external memory
status Conduit PHY calibration status interface
afi_reset_n Reset Output AFI reset interface
afi_clk Clock Output AFI clock interface
afi_half_clk Clock Output AFI half-rate clock interface
afi Conduit Altera PHY Interface (AFI)
emif_usr_reset_n Reset Output User clock domain reset interface
emif_usr_clk Clock Output User clock interface
emif_usr_reset_n_sec Reset Output User clock domain reset interface (for the secondary interface in ping-pong configuration)
emif_usr_clk_sec Clock Output User clock interface (for the secondary interface in ping-pong configuration)
cal_debug_reset_n Reset Input User calibration debug clock domain reset interface
cal_debug_clk Clock Input User calibration debug clock interface
cal_debug_out_reset_n Reset Output User calibration debug clock domain reset interface
cal_debug_out_clk Clock Output User calibration debug clock interface
clks_sharing_master_out Conduit Core clocks sharing master interface
clks_sharing_slave_in Conduit Core clocks sharing slave input interface
clks_sharing_slave_out Conduit Core clocks sharing slave output interface
ctrl_amm Avalon Memory-Mapped Slave Controller Avalon Memory-Mapped interface
ctrl_auto_precharge Conduit Controller auto-precharge interface
ctrl_user_priority Conduit Controller user-requested priority interface
ctrl_ecc_user_interrupt Conduit Controller ECC user interrupt interface
ctrl_ecc_readdataerror Conduit Controller ECC read data error indication interface
ctrl_ecc_status Conduit Controller ECC status interface
ctrl_mmr_slave Avalon Memory-Mapped Slave Controller MMR slave interface
hps_emif Conduit Conduit between Hard Processor Subsystem and memory interface
cal_debug Avalon Memory-Mapped Slave Calibration debug interface
cal_debug_out Avalon Memory-Mapped Master Calibration debug interface

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