External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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7.5.4.7. Clamshell Topology

In a DDR4 clamshell topology, SDRAM is arranged in two layers along either side of the chip, with individual memory devices opposite one another. This configuration allows for a smaller footprint than with fly-by topology, where memory devices are arranged on a single layer.

The small footprint of the clamshell topology requires less board space than fly-by topology. However, the close proximity of the memory devices in clamshell topology increases the complexity of the required device routing to prevent signal integrity problems.

Clamshell topology uses Address Mirroring to minimize undesired effects such as cross-talk, by splitting the chip select signal for each rank:

  • A chip select that accesses the top layer of components, which have not been mirrored.
  • A chip select that accesses the bottom layer of components, which have been mirrored.

The total number of chip selects required is double the interface's rank — for example, a single-rank memory interface requires two chip selects. The two chip selects are required for proper calibration of the interface, as a way of accounting for address mirroring. Because the I/O columns have 4 chip-select pins, an external memory interface for a clamshell memory topology has a maximum of 2 ranks, in contrast with the fly-by topology which supports up to 4 ranks.

The JEDEC specification JESD21-C defines address mirroring for DDR4 as shown in the table below.

Table 254.  Address Mirroring
Memory Controller Pin DRAM Pin (Non-Mirrored) DRAM Pin (Mirrored)
A3 A3 A4
A4 A4 A3
A5 A5 A6
A6 A6 A5
A7 A7 A8
A8 A8 A7
A11 A11 A13
A13 A13 A11
BA0 BA0 BA1
BA1 BA1 BA0
BG0 (1) BG0 BG1
BG1 (1) BG1 BG0
(1) BG0 and BG1 can be mirrored only when pin BG1 is present on the memory device.

Enabling Clamshell Topology in Your External Memory Interface

  1. Configure a single memory interface according to your requirements.
  2. Select Use clamshell layout on the General tab in the parameter editor.
  3. Set the number of chip-select pins equal to the number of ranks.
Note: Do not select the Address Mirror option in the parameter editor. Choosing a clamshell layout is sufficient to invoke address mirroring to configure the device.

Mapping

Table 255.  Single Rank
Rank Top/Bottom of Memory Device CS Pin on Memory Device CS Pin on FPGA
0 Top CS0 CS0
0 Bottom CS0 CS1
Table 256.  Dual Rank
Rank Top/Bottom of Memory Device CS Pin on Memory Device CS Pin on FPGA
0 Top CS0 CS0
0 Bottom CS0 CS2
1 Top CS1 CS1
1 Bottom CS1 CS3
Note: The single-rank clamshell and dual-rank clamshell pinouts are not interoperable.

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