External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public
Document Table of Contents

4.1.1.12. afi_reset_n for DDR3

AFI reset interface

Table 23.  Interface: afi_reset_nInterface type: Reset Output
Port Name Direction Description
afi_reset_n Output Reset for the AFI clock domain. Asynchronous assertion and synchronous deassertion

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