External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

13.2.1. Intel® IP Memory Model

Intel® memory IP autogenerates a generic simplified memory model that works in all cases. This simple read and write model is not designed or intended to verify all entered IP parameters or transaction requirements.

The Intel® -generated memory model may be suitable to evaluate some limited functional issues, but it does not provide comprehensive functional simulation.

Did you find the information on this page useful?

Characters remaining:

Feedback Message