External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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13.9.5.2.1. Address Generator Modes

Each of the six address generators can be configured to one of four modes.
  • Fixed: The address generator holds a constant value that is specified in the field’s corresponding TG_SEQ_START_ADDR_WR and TG_SEQ_START_ADDR_RD registers.
  • Random: The address generator starts at the value of the corresponding field’s TG_SEQ_START_ADDR_WR and TG_SEQ_START_ADDR_RD registers and generates a pseudorandom address for each instruction. (The pseudorandom address is generated by a Linear Feedback Shift Register (LFSR) and is guaranteed to not repeat for the entirety of the address generator width.)
  • Sequential: The address generator starts at the value of the corresponding field's TG_SEQ_START_ADDR_WR and TG_SEQ_START_ADDR_RD registers and increments by the value specified in the corresponding field’s TG_SEQ_ADDR_INCR register each instruction.
  • Unused: The address generator is deactivated and does not generate addresses. The address generator output is tied off to zero. Setting a field to this mode allows fewer than 6 address generators to be used.
Note: If a field is set to Random mode, the Start Address cannot be set to all 1s.

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