External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public
Document Table of Contents

4.1.5.17. cal_debug_clk for RLDRAM 3

User calibration debug clock interface

Table 155.  Interface: cal_debug_clkInterface type: Clock Input
Port Name Direction Description
cal_debug_clk Input User clock domain

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