External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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13.7.2.7.5. Debugging Read Deskew Calibration Failure

  1. Ensure that you specify the correct memory timing parameter, CAS, and Write CAS latency when generating the EMIF IP. An incorrect parameter value can cause data corruption.
  2. Determine which pins are failing.
    • If only certain DQ pins are failing, verify that there is no connectivity problem on the PCB.
    • If the same set of pins are failing on multiple PCBs, check for a possible problem with the board layout—for example, cross talk.
  3. Create design with smaller DQ width (that is, with only the failing DQS group) to reduce possible cross talk between adjacent I/O lanes.
  4. Probe the stability of the VTT power rail when running the calibration. An unstable VTT power rail can cause the wrong command to be received by the memory component.
  5. Probe the stability of the VCCIO power rail when running calibration.
  6. Test the design at lower frequencies and determine whether there is a frequency at which it passes.
  7. Retest the failing board after eliminating the dependence on ODT signals. The following settings in the EMIF IP eliminate the dependence on ODT signals:
    • Dynamic ODT (Rtt_WR) value = Dynamic ODT off.
    • ODT Rtt nominal value = ODT Disable.
    • Output drive strength setting = RZQ/7 (34 ohm)
    • Rtt Park = RZQ /3 (80 Ohm)

    If you have enabled the Unified Calibration Debug Toolkit in your design, you can change the above settings on the Calibrate Terminations tab, without recompiling your design

    Figure 153. Changing Termination Settings with the Unified Calibration Debug Toolkit
    Figure 154. Changing Termination Setting when Regenerating EMIF IP – Recompilation Required

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