External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public
Document Table of Contents

4.1.2.20. emif_usr_clk_sec for DDR4

User clock interface (for the secondary interface in ping-pong configuration)

Table 68.  Interface: emif_usr_clk_secInterface type: Clock Output
Port Name Direction Description
emif_usr_clk_sec Output User clock domain. Intended for the secondary interface in a ping-pong configuration.

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