13.3.1. Evaluating FPGA Timing Issues
- The .sdc files are incorrectly added to the Intel® Quartus® Prime project
- Intel® Quartus® Prime analysis and synthesis settings are not correct
- Intel® Quartus® Prime Fitter settings are not correct
For all of these issues, refer to the correct user guide for more information about recommended settings and follow these steps:
- Ensure that the IP generated .sdc files are listed in the Intel® Quartus® Prime Timing Analyzer files to include in the project window.
- Ensure that Analysis and Synthesis Settings are set to Optimization Technique Speed.
- Ensure that Fitter Settings are set to Fitter Effort Standard Fit.
- Use Timing Analyzer Report Ignored Constraints, to ensure that .sdc files are successfully applied.
- Use Timing Analyzer Report Unconstrained Paths, to ensure that all critical paths are correctly constrained.
More complex timing problems can occur if any of the following conditions are true:
- The design includes multiple PHY or core projects
- Devices where the resources are heavily used
- The design includes wide, distributed, maximum performance interfaces in large die sizes
Any of the above conditions can lead to suboptimal placement results when the PHY or controller are distributed around the FPGA. To evaluate such issues, simplify the design to just the autogenerated example top-level file and determine if the core meets timing and you see a working interface. Failure implies that a more fundamental timing issue exists. If the standalone design passes core timing, evaluate how this placement and fit is different than your complete design.
Use Logic Lock (Standard)regions, or design partitions to better define the placement of your memory controllers. When you have your interface standalone placement, repeat for additional interfaces, combine, and finally add the rest of your design.
Additionally, use fitter seeds and increase the placement and router effort multiplier.
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