5.3.2. Abstract PHY Simulation
Abstract PHY reduces simulation time by two mechanisms:
- The Nios processor has been disabled and is replaced by HDL forces that are applied at the beginning of simulation. The HDL forces are a minimum set of registers that configures the memory interface for simulation. The write and read latency values applied by the HDL forces are not representative of the post-calibration values applied to the memory interface running on hardware. However, as long as the customer logic is Avalon® and AFI-compliant, these values allow for successful RTL simulation.
- The abstract PHY eliminates the need for full-speed clocks and therefore simulation of the Abstract PHY does not require full-speed clock simulation events.
To use the Abstract PHY, enable Simulation Options > Abstract PHY for fast simulation on the Diagnostic tab during EMIF IP generation. When you enable Abstract PHY, the EMIF IP is configured as shown below. The PHY RTL and external memory model are disconnected from the data path and in their place is the abstract PHY containing an internal memory array.
- You cannot observe the external memory device signals when you are using Abstract PHY.
- Abstract PHY does not reflect accurate latency numbers.
- Abstract PHY Simulation does not support user-initiated resets using the reset sequence described in User-requested Reset in Intel Stratix 10 EMIF IP.
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