External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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4.1.5.24. cal_debug_out for RLDRAM 3

Calibration debug interface

Table 162.  Interface: cal_debug_outInterface type: Avalon Memory-Mapped Master
Port Name Direction Description
cal_debug_out_waitrequest Input Wait-request is asserted when controller is busy
cal_debug_out_read Output Read request signal
cal_debug_out_write Output Write request signal
cal_debug_out_addr Output Address for the read/write request
cal_debug_out_read_data Input Read data
cal_debug_out_write_data Output Write data
cal_debug_out_byteenable Output Byte-enable for write data
cal_debug_out_read_data_valid Input Indicates whether read data is valid

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