External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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Document Table of Contents

3.4.1.3. Data Buffer Controller

The data buffer controller performs the following operations:
  • Manages the read and write access to the data buffers:
    • Provides the data storing pointers to the buffers when the write data is accepted or the read return data arrives.
    • Provides the draining pointer when the write data is dispatched to memory or the read data is read out of the buffer and sent back to users.
  • Satisfies the required write latency.
  • If ECC support is enabled, assists the main control path to perform read-modify-write.

Data reordering is performed with the data buffer controller and the data buffers.

Each I/O bank contains two data buffer controller blocks for the data buffer lanes that are split within each bank. To improve your timing, place the data buffer controller physically close to the I/O lanes.

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