External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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2. External Memory Interfaces Intel® Stratix® 10 FPGA IP Introduction

Intel's fast, efficient, and low-latency external memory interface (EMIF) intellectual property (IP) cores easily interface with today's higher speed memory devices.

You can easily implement the EMIF IP core functions through the Intel® Quartus® Prime software. The Intel® Quartus® Prime software also provides external memory toolkits that help you test the implementation of the IP in the FPGA.

The External Memory Interfaces Intel® Stratix® 10 FPGA IP (referred to hereafter as the Intel® Stratix® 10 EMIF IP) provides the following components:

  • A physical layer interface (PHY) which builds the data path and manages timing transfers between the FPGA and the memory device.
  • A memory controller which implements all the memory commands and protocol-level requirements.

For information on the maximum speeds supported by the external memory interface IP, refer to the External Memory Interface Spec Estimator.

Intel® Stratix® 10 EMIF IP Protocol and Feature Support

  • Supports DDR4, DDR3, and DDR3L protocols with hard memory controller and hard PHY.
  • Supports QDR-IV, QDR II + Xtreme, QDR II +, and QDR II using soft memory controller and hard PHY.
  • Supports RLDRAM 3 using third-party soft controller.
  • Supports UDIMM, RDIMM, LRDIMM and SODIMM memory devices.
  • Supports 3D Stacked Die for DDR4 devices.
  • Supports up to 4 physical ranks.
  • Supports Ping Pong PHY mode, allowing two memory controllers to share command, address, and control pins.
  • Supports error correction code (ECC) for both hard memory controller and soft memory controller.

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