Intel® Stratix® 10 General Purpose I/O User Guide

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ID 683518
Date 7/07/2021
Public
Document Table of Contents

1. Intel® Stratix® 10 I/O Overview

Updated for:
Intel® Quartus® Prime Design Suite 21.2
The Intel® Stratix® 10 general purpose I/O (GPIO) system consists of the I/O elements (IOE) and the GPIO Intel® FPGA IP.
  • The IOEs contain bidirectional I/O buffers and I/O registers located in LVDS I/O banks.
  • The GPIO IP core supports the GPIO components and features, including double data rate I/O (DDIO), delay chains, I/O buffers, control signals, and clocking.
  • Two of the LVDS I/O banks are shared with the Secure Device Manager (SDM).
  • For devices with Hard Processor System (HPS), three of the LVDS I/O banks are shared with the HPS SDRAM interface.
  • The 3 V I/O banks do not feature I/O registers and DDIOs.
  • The 3.3 V I/O bank is available in the HF35 package of the Intel® Stratix® 10 GX 400 and SX 400 devices.

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