Intel® Stratix® 10 General Purpose I/O User Guide

ID 683518
Date 7/07/2021

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3.9. Guideline: I/O Standards Limitation for Intel® Stratix® 10 GX 400 and SX 400

  • On the Intel® Stratix® 10 GX 400 or SX 400 device, do not use the following I/O standards in I/O banks 3A and 3D except in dedicated clock pins:
    • LVDS
    • Mini-LVDS
    • RSDS
  • Bank 3D has only 30 GPIO pins and supports only 1.8 V I/O standards.
  • Bank 3C supports only unidirectional single-ended I/O in 3.3 V or 3.0 V I/O standard.
  • In bank 3C, the control of I/O direction and features such as current strength is per eight-pin groups basis.
    • To identify the pin groups, refer to the Optional Function(s) column in device pin out files. For example, the group name is IO33_LS[<group index>]_[<pin index>].
    • As an example, if you configure any I/O pins from group LS1 as input, all the other pins in the group use the same setting. Similarly, if you use a pin in group LS0 as an output pin with 12 mA current strength, all pins in group LS0 apply the same setting.
    • You cannot configure input and output pins in the same group. You can only use all eight pins as input, or all eight pins as output.
  • If you use 3 V I/O standard in the design without assigning pin locations, the Intel® Quartus® Prime software automatically assigns the pins to bank 3C. If you want to assign the 3 V I/O standard to the 3 V I/O bank, specify the USE_AS_3V_GPIO Intel® Quartus® Prime assignment to the pin in the .qsf file.
Table 16.  Example of Eight-Pin Groups in Bank 3C
Pin Group Entry in Optional Function(s) Column Pin Name
LS1 IO33_LS1_0 Y2
IO33_LS1_1 AA2
IO33_LS1_2 AB1
IO33_LS1_3 AB2
IO33_LS1_4 AC1
IO33_LS1_5 AD1
IO33_LS1_6 AF2
IO33_LS1_7 AG2
LS0 IO33_LS0_0 U3
IO33_LS0_1 V3
IO33_LS0_2 U5
IO33_LS0_3 V4
IO33_LS0_4 W2
IO33_LS0_5 Y1
IO33_LS0_6 W3
IO33_LS0_7 W4

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