Intel® Stratix® 10 General Purpose I/O User Guide

ID 683518
Date 7/07/2021
Public
Document Table of Contents

2.3.8. Programmable Current Strength

You can use the programmable current strength to mitigate the effects of high signal attenuation that is caused by a long transmission line or a legacy backplane.
Note:

To use programmable current strength, you must specify the current strength assignment in the Intel® Quartus® Prime software. Without explicit assignments, the Intel® Quartus® Prime software uses these predefined default values:

  • All HSTL and SSTL Class I, and all non-voltage-referenced I/O standards—50 Ω RS OCT without calibration
  • All HSTL and SSTL Class II I/O standards—25 Ω RS OCT without calibration
  • POD12 I/O standard—34 Ω RS OCT without calibration
Table 8.  Programmable Current Strength Settings for Intel® Stratix® 10 DevicesThe output buffer for each Intel® Stratix® 10 device I/O pin has a programmable current strength control for the I/O standards listed in this table.
I/O Standard

IOH / IOL Current Strength Setting (mA)

Supported in FPGA

Supported in HPS 12

(SoC Devices Only)

Available Default Available Default
3.3 V LVTTL 13 12, 8, 4 12
3.3 V LVCMOS13 12, 8, 4 12
3.0 V LVTTL 3.3 V I/O bank13 12, 8, 4 12
3 V I/O bank 14 24, 20, 16, 12, 8, 4
3.0 V LVCMOS 3.3 V I/O bank13 12, 8, 4 12
3 V I/O bank14 24, 20, 16, 12, 8, 4
2.5 V LVCMOS 16, 12, 8, 4 12
1.8 V LVCMOS 16, 12, 10, 8, 6, 4, 2 12 12, 10, 8 12
1.5 V LVCMOS 12, 10, 8, 6, 4, 2 12
1.2 V LVCMOS 8, 6, 4, 2 8
SSTL-18 Class I 8, 6, 4 8
SSTL-18 Class II 8 8
SSTL-15 Class I 8, 6, 4 8
SSTL-15 Class II 8 8
SSTL-135 8, 6, 4 8
SSTL-125 8, 6, 4 8
SSTL-12 8, 6, 4 8
POD12 8, 6, 4 8
1.8 V HSTL Class I 12, 10, 8, 6, 4 8
1.8 V HSTL Class II 14 14
1.5 V HSTL Class I 12, 10, 8, 6, 4 8
1.5 V HSTL Class II 14 14
1.2 V HSTL Class I 8, 6, 4 8
Differential SSTL-18 Class I 8, 6, 4 8
Differential SSTL-18 Class II 8 8
Differential SSTL-15 Class I 8, 6, 4 8
Differential SSTL-15 Class II 8 8
Differential SSTL-135 12, 10, 8, 6, 4 8
Differential SSTL-125 12, 10, 8, 6, 4 8
Differential SSTL-12 Class I 12, 10, 8, 6, 4 8
Differential POD12 8, 6, 4 8
Differential 1.8 V HSTL Class I 12, 10, 8, 6, 4 8
Differential 1.8 V HSTL Class II 14 14
Differential 1.5 V HSTL Class I 12, 10, 8, 6, 4 8
Differential 1.5 V HSTL Class II 14 14
Differential 1.2 V HSTL Class I 8, 6, 4 8
Note: Intel recommends that you perform IBIS or SPICE simulations to determine the best current strength setting for your specific application.
12 The programmable current strength information for the HPS is preliminary.
13 Available only on I/O bank 3C of the HF35 package of the Intel® Stratix® 10 GX 400 and SX 400 devices. The current strength setting control is per eight-pin groups basis. To identify the pin groups, refer to the Optional Function(s) column in device pin out files. For example, the group name is IO33_LS[<group index>]_[<pin index>].
14 Programmable slew rate control is applicable only for current strength settings of 16 mA and above.

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