Intel® Stratix® 10 General Purpose I/O User Guide

ID 683518
Date 7/07/2021
Public

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4.1.2.2. Output and Output Enable Paths

The output delay element sends data to the pad through the output buffer.

Each LVDS I/O output path contains two stages of DDIOs, which are half-rate and full-rate.

The 3 V I/Os do not support DDIOs.

Figure 28. Simplified View of Single-Ended GPIO Output Path


Figure 29. Output Path Waveform in DDIO Mode with Half-Rate Conversion
Figure 30.  Simplified View of Output Enable Path


The difference between the output path and output enable (OE) path is that the OE path does not contain full-rate DDIO. To support packed-register implementations in the OE path, a simple register operates as full-rate DDIO. For the same reason, only one half-rate DDIO is present.

The OE path operates in the following three fundamental modes:

  • Bypass—the core sends data directly to the delay element, bypassing all DDIOs.
  • Packed Register—bypasses half-rate DDIO.
  • SDR output at half-rate—half-rate DDIOs convert data from full-rate to half-rate.

In Intel® Stratix® 10 devices, each 3 V I/O bank supports only two output enables (OE) for its eight single-ended I/Os.

Note: The GPIO Intel® FPGA IP and OCT Intel® FPGA IP support OCT during power up and user mode on single-directional input or output pins. The GPIO IP does not support dynamic OCT of bidirectional pins. For applications that require dynamic OCT control for bidirectional pins, refer to the related information.

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