Intel® Stratix® 10 General Purpose I/O User Guide

ID 683518
Date 7/07/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.3.2. Programmable IOE Delay

You can activate the programmable IOE delays to ensure zero hold time, minimize setup time, or increase clock-to-output time. This feature helps read and write timing margins because it minimizes the uncertainties between signals in the bus.

To ensure that the signals within a bus have the same delay going into or out of the device, each pin can have different delay values:

  • Delay from input pin to input register
  • Delay from output pin to output register

For more information about the programmable IOE delay specifications, refer to the device datasheet.

Did you find the information on this page useful?

Characters remaining:

Feedback Message