Intel® Stratix® 10 General Purpose I/O User Guide

ID 683518
Date 7/07/2021
Public

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3.5. Guideline: Intel® Stratix® 10 I/O Buffer During Power Up, Configuration, and Power Down

  • During device power up and device configuration, all GPIO pins are tri-stated with weak pull-up enabled.
  • During device power down, all I/O pins are in undetermined state and the pin signal is measured between GND and the VCCIO level.
  • At any point,the input signal sof an I/O pin must not exceed the maximum DC input voltage specified in the device datasheet.
Figure 24.  Intel® Stratix® 10 I/O Buffers Behavior


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