4.6.2. Guideline: Swap datain_h and datain_l Ports in Migrated IP
The GPIO IP core drives these ports to the output registers on these clock edges:
- datain_h—on the rising edge of outclock
- datain_l—on the falling edge of outclock
If you migrated your GPIO IP from Stratix® V, Arria® V, and Cyclone® V devices, swap the datain_h and datain_l ports when you instantiate the IP generated by the GPIO IP core.
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