Intel® Stratix® 10 General Purpose I/O User Guide

ID 683518
Date 7/07/2021
Document Table of Contents Full-Rate or Half-Rate DDIO Input Register

The input side of the full-rate and half-rate DDIO input registers are the same. You can properly constrain the system by using a virtual clock to model the off-chip transmitter to the FPGA.
Figure 35. Full-Rate or Half-Rate DDIO Input Register

Table 22.  Full-Rate or Half-Rate DDIO Input Register .sdc Command Examples
Command Command Example Description

create_clock -name virtual_clock -period "200 MHz"

create_clock -name ddio_in_clk -period "200 MHz" ddio_in_clk

Create clock setting for the virtual clock and the DDIO clock.

set_input_delay -clock virtual_clock 0.25 ddio_in_data

set_input_delay -add_delay -clock_fall -clock virtual_clock 0.25 ddio_in_data

Instruct the Timing Analyzer to analyze the positive clock edge and the negative clock edge of the transfer. Note the -add_delay in the second set_input_delay command.

set_false_path -fall_from virtual_clock -rise_to ddio_in_clk

set_false_path -rise_from virtual_clock -fall_to ddio_in_clk

Instruct the Timing Analyzer to ignore the positive clock edge to the negative edge triggered register, and the negative clock edge to the positive edge triggered register.

Note: The ck_hr frequency must be half the ck_fr frequency. If the I/O PLL drives the clocks, you can consider using the derive_pll_clocks .sdc command.

Did you find the information on this page useful?

Characters remaining:

Feedback Message