Intel® Stratix® 10 General Purpose I/O User Guide

ID 683518
Date 7/07/2021
Public

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2. Intel® Stratix® 10 I/O Architecture and Features

The I/O system of Intel® Stratix® 10 devices supports various I/O standards. In Intel® Stratix® 10 devices, the I/O pins are located in I/O banks. The I/O pins and I/O buffers have several programmable features.

The Intel® Stratix® 10 I/Os support the following features:

  • Single-ended, non-voltage-referenced, and voltage-referenced I/O standards
  • Low-voltage differential signaling (LVDS), RSDS, mini-LVDS, HSTL, HSUL, SSTL, and POD I/O standards
  • Serializer/deserializer (SERDES)
  • Programmable output current strength
  • Programmable slew rate
  • Programmable bus-hold
  • Programmable weak pull-up resistor
  • Programmable pre-emphasis for DDR4 and the LVDS output buffer
  • Programmable I/O delay
  • Programmable differential output voltage (VOD)
  • Programmable open-drain output
  • On-chip series termination (RS OCT) with and without calibration
  • On-chip parallel termination (RT OCT)
  • On-chip differential termination (RD OCT)
  • HSTL and SSTL input buffer with dynamic power down
  • Dynamic on-chip parallel termination for all I/O banks
  • Internally generated VREF with DDR4 calibration
Note: The information in this chapter is applicable to all Intel® Stratix® 10 variants, unless noted otherwise.

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