Intel® Stratix® 10 General Purpose I/O User Guide

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ID 683518
Date 7/07/2021
Public
Document Table of Contents

2.2.1. I/O Bank Architecture in Intel® Stratix® 10 Devices

In each LVDS I/O bank, there are four I/O lanes with 12 I/O pins in each lane. Other than the I/O lanes, each I/O bank also contains dedicated circuitries including the I/O PLL, DPA block, SERDES, hard memory controller, and I/O sequencer.

However, the DPA block and SERDES are not available in the following I/O banks in package HF35 of the following devices:

  • Intel® Stratix® 10 GX 400 and SX 400 devices—I/O banks 3A, 3C, and 3D
  • Intel® Stratix® 10 TX 400 devices—I/O banks 3A and 3D

In each 3 V or 3.3 V I/O bank, there are eight single-ended I/O buffers. The 3.3 V I/O bank in package HF35 of the Intel® Stratix® 10 GX 400 and SX 400 devices supports only unidirectional single-ended 3.3 V or 3.0 V I/O buffers. In the 3.3 V I/O bank, the pins form eight-pin groups. You can configure all eight pins in a group together as all input only or all output only. To identify the pin groups, refer to the Optional Function(s) column in device pin out files.

Figure 5. I/O Bank StructureThis figure shows an example of I/O banks in one Intel® Stratix® 10 device. The I/O banks availability and locations vary among Intel® Stratix® 10 devices.


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