2.2.1. I/O Bank Architecture in Intel® Stratix® 10 Devices
However, the DPA block and SERDES are not available in the following I/O banks in package HF35 of the following devices:
- Intel® Stratix® 10 GX 400 and SX 400 devices—I/O banks 3A, 3C, and 3D
- Intel® Stratix® 10 TX 400 devices—I/O banks 3A and 3D
In each 3 V or 3.3 V I/O bank, there are eight single-ended I/O buffers. The 3.3 V I/O bank in package HF35 of the Intel® Stratix® 10 GX 400 and SX 400 devices supports only unidirectional single-ended 3.3 V or 3.0 V I/O buffers. In the 3.3 V I/O bank, the pins form eight-pin groups. You can configure all eight pins in a group together as all input only or all output only. To identify the pin groups, refer to the Optional Function(s) column in device pin out files.
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