Intel® Stratix® 10 General Purpose I/O User Guide

ID 683518
Date 7/07/2021
Public
Document Table of Contents

4.1.2.1. Input Path

The pad sends data to the input buffer, and the input buffer feeds the delay element. After the data goes to the output of the delay element, the programmable bypass multiplexers select the features and paths to use.
Each LVDS I/O input path contains two stages of DDIOs, which are full-rate and half-rate.

The 3 V I/Os do not support DDIOs.

Figure 26. Simplified View of Single-Ended GPIO Input Path


  1. The pad receives data.
  2. DDIO IN (1) captures data on the rising and falling edges of ck_fr and sends the data, signals (A) and (B) in the following waveform figure, at single data rate.
  3. DDIO IN (2) and DDIO IN (3) halve the data rate.
  4. dout[3:0] presents the data as a half-rate bus.
Figure 27. Input Path Waveform in DDIO Mode with Half-Rate Conversion

In this figure, the data goes from full-rate clock at double data rate to half-rate clock at single data rate. The data rate is divided by four and the bus size is increased by the same ratio. The overall throughput through the GPIO IP core remains unchanged.

The actual timing relationship between different signals may vary depending on the specific design, delays, and phases that you choose for the full-rate and half-rate clocks.



Note: The GPIO Intel® FPGA IP and OCT Intel® FPGA IP support OCT during power up and user mode on single-directional input or output pins. The GPIO IP does not support dynamic OCT of bidirectional pins. For applications that require dynamic OCT control for bidirectional pins, refer to the related information.

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