22.214.171.124. Input Path
The 3 V I/Os do not support DDIOs.
- The pad receives data.
- DDIO IN (1) captures data on the rising and falling edges of ck_fr and sends the data, signals (A) and (B) in the following waveform figure, at single data rate.
- DDIO IN (2) and DDIO IN (3) halve the data rate.
- dout[3:0] presents the data as a half-rate bus.
In this figure, the data goes from full-rate clock at double data rate to half-rate clock at single data rate. The data rate is divided by four and the bus size is increased by the same ratio. The overall throughput through the GPIO IP core remains unchanged.
The actual timing relationship between different signals may vary depending on the specific design, delays, and phases that you choose for the full-rate and half-rate clocks.
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