1. Intel® Stratix® 10 I/O Overview 2. Intel® Stratix® 10 I/O Architecture and Features 3. Intel® Stratix® 10 I/O Design Considerations 4. Intel® Stratix® 10 I/O Implementation Guides 5. GPIO Intel® FPGA IP Reference 6. Intel® Stratix® 10 General Purpose I/O User Guide Archives 7. Document Revision History for Intel® Stratix® 10 General Purpose I/O User Guide
2.1. I/O Standards and Voltage Levels in Intel® Stratix® 10 Devices 2.2. I/O Element Structure in Intel® Stratix® 10 Devices 2.3. Programmable IOE Features in Intel® Stratix® 10 Devices 2.4. On-Chip I/O Termination in Intel® Stratix® 10 Devices 2.5. External I/O Termination for Intel® Stratix® 10 Devices
3.1. Guideline: VREF Sources and VREF Pins 3.2. Guideline: Observe Device Absolute Maximum Rating for 3.0 V Interfacing 3.3. Guideline: Voltage-Referenced and Non-Voltage Referenced I/O Standards 3.4. Guideline: Do Not Drive I/O Pins During Power Sequencing 3.5. Guideline: Intel® Stratix® 10 I/O Buffer During Power Up, Configuration, and Power Down 3.6. Guideline: Maximum DC Current Restrictions 3.7. Guideline: Use Only One Voltage for All 3 V I/O Banks 3.8. Guideline: I/O Standards Limitation for Intel® Stratix® 10 TX 400 3.9. Guideline: I/O Standards Limitation for Intel® Stratix® 10 GX 400 and SX 400
1.1. Intel® Stratix® 10 I/O and Differential I/O Buffers
The general purpose I/Os (GPIOs) consist of the following I/O banks:
- LVDS I/O bank—supports differential and single-ended I/O standards up to 1.8 V. The LVDS I/O pins form pairs of true differential LVDS channels. Each pair supports a parallel input/output termination between the two pins. You can use each LVDS channel as transmitter only or receiver only. Each LVDS channel supports transmit SERDES and receive SERDES with DPA circuitry. For example, if you use 30 channels of the available 72 channels as transmitters, you can use the remaining 42 channels as receivers.
- 3 V I/O bank—supports single-ended LVCMOS and LVTTL I/O standards up to 3.0 V. In Intel® Stratix® 10 devices, each 3 V I/O bank supports only two output enables (OE) for its eight single-ended I/Os. Single-ended I/Os within this I/O bank support all programmable I/O element (IOE) features except:
- Programmable pre-emphasis
- RD on-chip termination (OCT)
- Calibrated RS and RT OCT
- Internal VREF generation
- Dynamic OCT
- 3.3 V I/O bank—supports single-ended LVCMOS and LVTTL I/O standards at 3.3 V and 3.0 V. This feature is available only in the HF35 package of the Intel® Stratix® 10 GX 400 and SX 400 devices. The 3.3 V I/O buffer is unidirectional. You can configure the I/O pins in the bank in preset groups of eight pins—as all input pins or all output pins. The bank supports the following features:
- As input—programmable pull up resistor
- As output—programmable current strength
Note: The 3 V I/O banks in Intel® Stratix® 10 devices do not support the DDIO feature of the GPIO IP core. Bypass the DDIO if you use an I/O standard supported only by 3 V I/O banks, such as 3.0 V LVCMOS. To bypass the DDIO feature, set the Register mode of the GPIO IP core to none.
Note: The 3 V I/O banks are located on the Intel® Stratix® 10 transceiver tiles. These banks are available only on the L-tile and H-tile transceiver tiles.
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