Intel® Stratix® 10 General Purpose I/O User Guide

ID 683518
Date 7/07/2021
Public
Document Table of Contents

2.1.1. Intel® Stratix® 10 I/O Standards Support

Table 1.   Intel® Stratix® 10 Devices I/O Standards Support for FPGA I/O—Preliminary
I/O Standard I/O Buffer Type Support Application Standard Support
LVDS I/O 3 V I/O1 2 3.3 V I/O3
3.3 V LVTTL/3.3 V LVCMOS No No Yes General purpose JESD8-B
3.0 V LVTTL/3.0 V LVCMOS No Yes 4 Yes General purpose JESD8-B
2.5 V LVCMOS No Yes 5 No General purpose JESD8-5
1.8 V LVCMOS Yes Yes 5 No General purpose JESD8-7
1.5 V LVCMOS Yes Yes 5 No General purpose JESD8-11
1.2 V LVCMOS Yes Yes 5 No General purpose JESD8-12
SSTL-18 Class I and Class II Yes No No Flash interface JESD8-15
SSTL-15 Class I and Class II Yes No No DDR3
SSTL-15 Yes No No DDR3 JESD79-3D
SSTL-135 Yes No No DDR3L
SSTL-125 6 Yes No No QDR-IV
SSTL-12 Yes No No RLDRAM 3, QDR-IV
POD12 Yes No No DDR4, QDR-IV JESD8-24
1.8 V HSTL Class I and Class II Yes No No DDR II+, QDR II+, and RLDRAM 2 JESD8-6
1.5 V HSTL Class I and Class II Yes No No DDR II+, QDR II+, QDR II, and RLDRAM 2 JESD8-6
1.2 V HSTL Class I and Class II Yes No No QDR-IV, General purpose JESD8-16A
HSUL-12 Yes No No LPDDR2, LPDDR3
Differential SSTL-18 Class I and Class II Yes No No General purpose JESD8-15
Differential SSTL-15 Class I and Class II Yes No No DDR3
Differential SSTL-15 Yes No No DDR3 JESD79-3D
Differential SSTL-135 Yes No No DDR3L
Differential SSTL-1256 Yes No No General purpose
Differential SSTL-12 Yes No No RLDRAM 3
Differential POD12 Yes No No DDR4 JESD8-24
Differential 1.8 V HSTL Class I and Class II Yes No No DDR II+, QDR II+, and RLDRAM 2 JESD8-6
Differential 1.5 V HSTL Class I and Class II Yes No No DDR II+, QDR II+, QDR II, and RLDRAM 2 JESD8-6
Differential 1.2 V HSTL Class I and Class II Yes No No General purpose JESD8-16A
Differential HSUL-12 Yes No No LPDDR2, LPDDR3
LVDS 7 Yes No No SGMII, SFI, SPI ANSI/TIA/EIA-644
Mini-LVDS 7 Yes No No SGMII, SFI, SPI
RSDS7 Yes No No SGMII, SFI, SPI
LVPECL Yes No No SGMII, SFI, SPI
Note: To use the 1.2 V, 1.5 V, 1.8 V, 2.5, or 3.0 V I/O standards in the 3 V I/O bank, you must set the USE_AS_3V_GPIO assignment to the I/O pin. In the Intel® Quartus® Prime Settings File (.qsf), specify the following assignment: set_instance_assignment -name USE_AS_3V_GPIO ON -to <your pin name>
Table 2.   Intel® Stratix® 10 SX Devices I/O Standards Support for HPS I/O—Preliminary
I/O Standard Application Standard Support
1.8 V LVCMOS General purpose JESD8-7
1 Available only on L-tile and H-tile transceiver tiles.
2 When a transceiver tile is powered down, the tile's 3 V I/O bank is not available.
3 Available only on I/O bank 3C of the HF35 package of the Intel® Stratix® 10 GX 400 and SX 400 devices.
4 For the HF35 package of the Intel® Stratix® 10 GX 400 and SX 400 devices, the Intel® Quartus® Prime software automatically implements the 3 V I/O standard using I/O bank 3C. For H-tile and L-tile devices, you must set the USE_AS_3V_GPIO Intel® Quartus® Prime assignment to the pin.
5 You must set the USE_AS_3V_GPIO Intel® Quartus® Prime assignment to the pin.
6 Even though the Intel® Stratix® 10 I/O buffers support various I/O standards for memory application, Intel validates and support only IPs for memory interfaces listed in Performance Support Summary, Intel® Stratix® 10 External Memory Interfaces User Guide.
7 Supported only on dedicated clock pin in I/O banks 3A and 3D of the Intel® Stratix® 10 TX 400, GX 400, and SX 400 devices.

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