Intel® Stratix® 10 General Purpose I/O User Guide

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ID 683518
Date 7/07/2021
Public
Document Table of Contents

4.1. GPIO Intel® FPGA IP

The GPIO IP core supports the GPIO components and features of the Intel® Stratix® 10 device family. You can use the Intel® Quartus® Prime parameter editor to configure the GPIO IP core.

Components of the GPIO IP core:

  • Double data rate input/output (DDIO)—doubles or halves the data-rate of a communication channel
  • Delay chains—configure the delay chains to perform specific delay and assist in I/O timing closure
  • I/O buffers—connect the pads to the FPGA
Note: The 3 V I/O banks in Intel® Stratix® 10 devices do not support the DDIO feature of the GPIO IP core. Bypass the DDIO if you use an I/O standard supported only by 3 V I/O banks, such as 3.0 V LVCMOS. To bypass the DDIO feature, set the Register mode of the GPIO IP core to none.

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