Intel® Stratix® 10 General Purpose I/O User Guide

ID 683518
Date 7/07/2021
Document Table of Contents

4.4. GPIO Intel® FPGA IP Design Examples

The GPIO IP core can generate design examples that match your IP configuration in the parameter editor. You can use these design examples as references for instantiating the IP core and the expected behavior in simulations.

You can generate the design examples from the GPIO IP core parameter editor. After you setting the parameters that you want, click Generate Example Design. The IP core generates the design example source files in the directory you specify.

Figure 37. Source Files in the Generated Design Example Directory

Note: The .qsys files are for internal use during design example generation only. You cannot edit these .qsys files.

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