External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

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ID 683741
Date 3/11/2022
Public
Document Table of Contents

4.1.1.35. cal_debug for DDR3

Calibration debug interface

Table 46.  Interface: cal_debugInterface type: Avalon Memory-Mapped Slave
Port Name Direction Description
cal_debug_waitrequest Output Wait-request is asserted when controller is busy
cal_debug_read Input Read request signal
cal_debug_write Input Write request signal
cal_debug_addr Input Address for the read/write request
cal_debug_read_data Output Read data
cal_debug_write_data Input Write data
cal_debug_byteenable Input Byte-enable for write data
cal_debug_read_data_valid Output Indicates whether read data is valid

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